#define LCD_FRAME_BUFFER_LAYER1 LCD_FRAME_BUFFER\r
#define CONVERTED_FRAME_BUFFER (LCD_FRAME_BUFFER+0x260000)\r
\r
+static void SystemClock_Config(void)\r
+{\r
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;\r
+ RCC_OscInitTypeDef RCC_OscInitStruct;\r
+\r
+ /* Enable Power Control clock */\r
+ __PWR_CLK_ENABLE();\r
+\r
+ /* The voltage scaling allows optimizing the power consumption when the device is\r
+ clocked below the maximum system frequency, to update the voltage scaling value\r
+ regarding system frequency refer to product datasheet. */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+ /* Enable HSE Oscillator and activate PLL with HSE as source */\r
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r
+ RCC_OscInitStruct.PLL.PLLM = 8;\r
+ RCC_OscInitStruct.PLL.PLLN = 336;\r
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;\r
+ RCC_OscInitStruct.PLL.PLLQ = 7;\r
+ HAL_RCC_OscConfig (&RCC_OscInitStruct);\r
+\r
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2\r
+ clocks dividers */\r
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\r
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;\r
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;\r
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);\r
+}\r
+\r
+\r
void hw_init(void)\r
{\r
- pll_init();\r
+ SystemInit();\r
HAL_Init();\r
+ SystemClock_Config();\r
\r
/* Initialize the LEDs */\r
BSP_LED_Init(LED3);\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.1\r
+ * @date 26-February-2014\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\r
+ *\r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f4xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F4xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f4xx_hal.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Variables\r
+ * @{\r
+ */\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 16000000;\r
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the FPU setting, vector table location and External memory \r
+ * configuration.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value\r
+ * depends on the application requirements), user has to ensure that HSE_VALUE\r
+ * is same as the real frequency of the crystal used. Otherwise, this function\r
+ * may have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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