Some work on rationalising and tidying up timing logging.
authorCarl Hetherington <cth@carlh.net>
Wed, 19 Aug 2015 00:21:15 +0000 (01:21 +0100)
committerCarl Hetherington <cth@carlh.net>
Wed, 19 Aug 2015 00:21:15 +0000 (01:21 +0100)
commitd482f805bc113ddf4c504e86125c648113321c8a
tree0be2f15cd7f5462c7ad728eb75f1530ac41f0520
parentc450fb19ea21dba0a6cade81e829262e7078e9df
Some work on rationalising and tidying up timing logging.
hacks/analog.py
src/lib/dcp_video.cc
src/lib/encoder.cc
src/lib/writer.cc