2 Copyright (C) 2012 Paul Davis
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include "libpbd-config.h"
22 #define _XOPEN_SOURCE 600
23 #include <cstring> // for memset
28 #ifdef PLATFORM_WINDOWS
32 #include "pbd/compose.h"
34 #include "pbd/error.h"
41 FPU* FPU::_instance (0);
43 #if ( (defined __x86_64__) || (defined __i386__) || (defined _M_X64) || (defined _M_IX86) ) // ARCH_X86
44 #ifndef PLATFORM_WINDOWS
46 /* use __cpuid() as the name to match the MSVC/mingw intrinsic */
49 __cpuid(int regs[4], int cpuid_leaf)
51 int eax, ebx, ecx, edx;
65 :"=m" (eax), "=m" (ebx), "=m" (ecx), "=m" (edx)
68 #if !defined(__i386__)
79 #endif /* !PLATFORM_WINDOWS */
84 _xgetbv (uint32_t xcr)
87 /* it would be nice to make this work on OS X but as long we use veclib,
88 we don't really need to know about SSE/AVX on that platform.
93 __asm__ volatile ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (xcr));
94 return (static_cast<uint64_t>(edx) << 32) | eax;
100 // '_xgetbv()' was only available from VC10 onwards
101 __declspec(noinline) static uint64_t
102 _xgetbv (uint32_t xcr)
106 // N.B. The following would probably work for a pre-VC10 build,
107 // although it might suffer from optimization issues. We'd need
108 // to place this function into its own (unoptimized) source file.
111 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0 /*xgetbv*/
115 #endif /* !COMPILER_MSVC */
116 #endif /* ARCH_X86 */
118 #ifndef _XCR_XFEATURE_ENABLED_MASK
119 #define _XCR_XFEATURE_ENABLED_MASK 0
143 error << _("FPU object instantiated more than once") << endmsg;
146 #if !( (defined __x86_64__) || (defined __i386__) || (defined _M_X64) || (defined _M_IX86) ) // !ARCH_X86
147 /* Non-Intel architecture, nothing to do here */
151 /* Get the CPU vendor just for kicks */
153 // __cpuid with an InfoType argument of 0 returns the number of
154 // valid Ids in CPUInfo[0] and the CPU identification string in
155 // the other three array elements. The CPU identification string is
156 // not in linear order. The code below arranges the information
157 // in a human readable form. The human readable order is CPUInfo[1] |
158 // CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped
159 // before using memcpy to copy these three array elements to cpu_string.
165 __cpuid (cpu_info, 0);
167 int num_ids = cpu_info[0];
168 std::swap(cpu_info[2], cpu_info[3]);
169 memcpy(cpu_string, &cpu_info[1], 3 * sizeof(cpu_info[1]));
170 cpu_vendor.assign(cpu_string, 3 * sizeof(cpu_info[1]));
172 info << string_compose (_("CPU vendor: %1"), cpu_vendor) << endmsg;
176 /* Now get CPU/FPU flags */
178 __cpuid (cpu_info, 1);
180 if ((cpu_info[2] & (1<<27)) /* OSXSAVE */ &&
181 (cpu_info[2] & (1<<28) /* AVX */) &&
182 ((_xgetbv (_XCR_XFEATURE_ENABLED_MASK) & 0x6) == 0x6)) { /* OS really supports XSAVE */
183 info << _("AVX-capable processor") << endmsg;
184 _flags = Flags (_flags | (HasAVX) );
187 if (cpu_info[3] & (1<<25)) {
188 _flags = Flags (_flags | (HasSSE|HasFlushToZero));
191 if (cpu_info[3] & (1<<26)) {
192 _flags = Flags (_flags | HasSSE2);
195 /* Figure out CPU/FPU denormal handling capabilities */
197 if (cpu_info[3] & (1 << 24)) {
201 /* DAZ wasn't available in the first version of SSE. Since
202 setting a reserved bit in MXCSR causes a general protection
203 fault, we need to be able to check the availability of this
204 feature without causing problems. To do this, one needs to
205 set up a 512-byte area of memory to save the SSE state to,
206 using fxsave, and then one needs to inspect bytes 28 through
207 31 for the MXCSR_MASK value. If bit 6 is set, DAZ is
208 supported, otherwise, it isn't.
211 #ifndef HAVE_POSIX_MEMALIGN
212 # ifdef PLATFORM_WINDOWS
213 fxbuf = (char **) _aligned_malloc (sizeof (char *), 16);
215 *fxbuf = (char *) _aligned_malloc (512, 16);
218 # warning using default malloc for aligned memory
219 fxbuf = (char **) malloc (sizeof (char *));
221 *fxbuf = (char *) malloc (512);
225 (void) posix_memalign ((void **) &fxbuf, 16, sizeof (char *));
227 (void) posix_memalign ((void **) fxbuf, 16, 512);
231 memset (*fxbuf, 0, 512);
248 uint32_t mxcsr_mask = *((uint32_t*) &((*fxbuf)[28]));
250 /* if the mask is zero, set its default value (from intel specs) */
252 if (mxcsr_mask == 0) {
256 if (mxcsr_mask & (1<<6)) {
257 _flags = Flags (_flags | HasDenormalsAreZero);
260 #if !defined HAVE_POSIX_MEMALIGN && defined PLATFORM_WINDOWS
261 _aligned_free (*fxbuf);
262 _aligned_free (fxbuf);
269 /* finally get the CPU brand */
271 __cpuid (cpu_info, 0x80000000);
273 const int parameter_end = 0x80000004;
276 if (cpu_info[0] >= parameter_end) {
277 char* cpu_string_ptr = cpu_string;
279 for (int parameter = 0x80000002; parameter <= parameter_end &&
280 cpu_string_ptr < &cpu_string[sizeof(cpu_string)]; parameter++) {
281 __cpuid(cpu_info, parameter);
282 memcpy(cpu_string_ptr, cpu_info, sizeof(cpu_info));
283 cpu_string_ptr += sizeof(cpu_info);
285 cpu_brand.assign(cpu_string, cpu_string_ptr - cpu_string);
286 info << string_compose (_("CPU brand: %1"), cpu_brand) << endmsg;
289 #endif /* !ARCH_X86 */